This invention relates generally to digital data communications systems, and more particularly to the recovery of clock and data signals from serial digital data streams.
In many communications systems, digital data is often transmitted without a clock signal that would otherwise indicate the sequence of data bits. This increases available bandwidth over a transmission medium through avoidance of transmission of an attendant clock signal. A non-return to zero (NRZ) data format is an example of a transmission scheme that does not require that a clock be transmitted along with the data.
The data signals, in the form of bits, are transmitted approximate a predetermined transmission rate. The transmission rate is determined by a clock in a data transmitter. Initially, it might seem possible to simply equip a data receiver with a clock operating at the same frequency as the clock in the data transmitter. Thus, data would automatically be received at the same rate that it was transmitted. However, even very small variations in the frequency of either of the two clocks would likely render this scheme unusable. A number of factors can lead to clock frequency variation, such as the age of the clocks and associated components, manufacturing tolerances, and environmental conditions such as temperature. In addition, if the clocks differ in phase by any substantial amount, data sampling could occur during data transitions, with resulting errors.
Since the data signals are transmitted approximate a predetermined rate, it is possible to extract timing information from the data stream itself. Using the data signal to extract timing information can be accomplished using phase locked loop approaches. The extracted timing information is used to recover the sequence of the bits in an incoming serial data transmission.
As demand for high speed communications continues to grow, multiple data streams are often used to transmit information. In order to simultaneously recover the information contained in each data stream, the timing information needs to be extracted from each data stream. This generally requires multiple phase locked loops, as at least one is ordinarily used for each data stream with the phased locked loops including clock generators such as oscillators, phase detectors, filters, etc. For communication systems having multiple data streams received by a single chip, the number of such elements that can be effectively placed on a single chip is constrained by area constraints, the package technology used, and by the thermal requirements of the system.